- 演讲人: Marc Casas(BSC,LEADING RESEARCHER)
- 时间:2024年10月14日10:00(北京时间)
- 地点:浙江大学紫金港校区行政楼1417报告厅
Talk Abstract:
This talk will show how
state-of-the-art proposals to compute convolutions on architectures with CPUs
supporting SIMD instructions deliver poor performance for long SIMD lengths due
to frequent cache conflict misses. The talk will propose new algorithmic
approaches to mitigate the limitation of state-of-the-art proposals via the
adaptation of the amount of computation exposed to the microarchitecture to
mitigate cache misses, and the redefinition of the activation memory layout to
improve the memory access pattern. These algorithmic approaches will motivate
the Matrix Tile Extension (MTE), a novel matrix Instruction-Set Architecture
(ISA) that completely decouples the instruction set architecture from the
microarchitecture and seamlessly interacts with existing vector ISAs. MTE
incurs minimal implementation overhead since it only requires a few additional
instructions and a 64-bit Control Status Register (CSR) to keep its state, and
beats the best state-of-the-art matrix ISA by 1.20x.
Bio:
Marc Casas is a technical research lead at the Barcelona Supercomputing Center (BSC) and lecturer at the Universitat Politècnica de Catalunya (UPC). His research lays between computer architecture (e.g. memory address translation, vector architectures) and high-performance computing (e.g. sparse linear algebra, parallel deep learning). He is the technical lead of the SONAR (parallel SOftware and New ARchitectures) research group, composed of PhD students, engineers, and postdocs. Marc has lead BSC contributions to several european projects (Mont-Blanc2020, European Processor Initiative, etc.), and research collaborations with Intel and IBM.
Marc has been at BSC since 2013. He was a postdoctoral
research scholar at the Lawrence Livermore National Laboratory (LLNL) from 2010
to 2013. He received the Marie Curie and Ramón y Cajal Fellowships on 2014 and
2018, respectively. He obtained a 5-years degree in mathematics in 2004,
and a PhD degree in Computer Science in 2010 from the Universitat Politècnica
de Catalunya (UPC).